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Hyunyoon Cho

Hyunyoon Cho

Seoul National University - Seoul / South Korea
Engineering & Technology / Electrical & Electronic Engineering
AD Scientific Index ID: 340886
서울대학교
person_outline Hyunyoon Cho's MOST POPULAR ARTICLES
1-) A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 128 I/Os Using TSV Based Stacking IEEE Journal of Solid-State Circuits 47 (1), 107-116, 2011
2-) Defect analysis and cost-effective resilience architecture for future DRAM devices 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
3-) A 1.2 V 30nm 1.6 Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme 2012 IEEE International Solid-State Circuits Conference, 44-46, 2012
4-) Leveraging Power-performance Relationship of Energy-efficient Modern DRAM Devices IEEE Access, 2018
5-) 23.1 a 7.5 Gb/s/pin LPDDR5 SDRAM with WCK clocking and non-target ODT for high speed and with DVFS, internal data copy, and deep-sleep mode for low power 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 378-380, 2019