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Rishu Chaujar

Rishu Chaujar

Delhi Technological University - New Delhi / India
Engineering & Technology / Nanoscience and Nanotechnology
AD Scientific Index ID: 350728
दिल्ली प्रौद्योगिकी विश्वविद्यालय
person_outline Rishu Chaujar's MOST POPULAR ARTICLES
1-) Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability IEEE Transactions on Device and Materials Reliability 16 (2), 227-234, 2016
2-) Numerical Simulation of N+Source Pocket PIN-GAA-Tunnel FET: Impact of Interface Trap Charges and Temperature IEEE Transactions on Electron Devices 64 (4), 1482-1488, 2017
3-) Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor Microelectronics Reliability 51 (3), 587-596, 2011
4-) Gate drain underlapped-PNIN-GAA-TFET for comprehensively upgraded analog/RF performance Superlattices and Microstructures 102, 17-26, 2017
5-) Numerical simulations: Toward the design of 27.6% efficient four-terminal semi-transparent perovskite/SiC passivated rear contact silicon tandem solar cell Superlattices and Microstructures 100, 656-666, 2016