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T Ghani

T Ghani

Intel Corporation - California / United States
Engineering & Technology / Electrical & Electronic Engineering
AD Scientific Index ID: 4376588
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person_outline T Ghani's MOST POPULAR ARTICLES
1-) A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging 2007 IEEE international electron devices meeting, 247-250, 2007
2-) A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors 2012 symposium on VLSI technology (VLSIT), 131-132, 2012
3-) A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors IEEE International Electron Devices Meeting 2003, 11.6. 1-11.6. 3, 2003
4-) A 90-nm logic technology featuring strained-silicon IEEE Transactions on electron devices 51 (11), 1790-1797, 2004
5-) A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size 2014 IEEE international electron devices meeting, 3.7. 1-3.7. 3, 2014